Neural Networks-Based Routing Congestion Prediction Using Initial Layout Parameters

Abstract: This paper considers the problem of congestion map prediction at the pre-routing stage of VLSI layout design of digital blocks by applying neural network models. Early prediction of congestion will allow the VLSI design engineer to modify floorplan, macro placement and input-output port placement to prevent interconnect routing issues at later stages. This, in turn, reduces the number of EDA tool runs and the overall circuit design runtime. In this work we propose the use of initial layout parameters as input channels in the U-Net architecture, which was not considered in other works. These parameters enhance the model’s ability to predict routing congestion with greater accuracy. As a result, we achieved a Pearson correlation with target maps of around 0.83, indicating strong model performance. © Allerton Press, Inc. 2025.